The use of fault resilient booting is known in the art and for example is described in U.S. Pat. No. 5,790,850. As described therein and as shown in FIG. 1, a multiprocessor system includes a number of processors 10-13 each of which include a local advance programmable interrupt controller (APIC) 14-17. The local APIC units are connected through an APIC 19 bus. An input/output APIC unit 28 is also connected to this bus. A processor bus 20 connects the processors and the memory.
In this system, when power is initially applied to the processors one of the processors is designated the bootstrap processor. One of the processors can be designated in the hardware for this function. The other processors are classified as application processors. Each of the processors undergoes a built in self test when power is initially applied. If the processor is faulty for any reason, it stores a status flag to indicate this. If the bootstrap processor is faulty, it is necessary to designate one of the application processors to handle the bootstrap function instead. U.S. Pat. No. 5,790,850 shows one method for doing this where application processors that have been tested to be good are successively examined. If all tests are passed, that application processor is designated as the bootstrap processor and that function is removed from the original bootstrap processor.
In systems of this type, the fault resilient booting is implemented in servers using the basic input output system (BIOS), the baseboard management controller (BMC) and other hardware to follow this procedure when the bootstrap processor fails. Most of this function is implemented in the baseboard management controller chip. However, the inclusion of this chip adds to the cost of the system. While this is not a problem for more expensive systems, in low cost servers, it is desirable to reduce the cost of the system.